1. Field of the Invention
The present invention relates to a master electronics card in a backplane-based communications system and, more particularly, to a master electronics card with an adaptive bandwidth circuit that substantially increases the throughput efficiency.
2. Description of the Related Art
A backplane-based communications system is a system that electrically connects together a number of electronics cards, such as xDSL line cards, via a multi-drop transmission line (MDTL) that runs through the backplane. Each of the electronics cards includes transceivers that receive information from, and transmit information to, the MDTL.
The electronics cards send information to, and receive information from, the MDTL in accordance with the rules defined by a communications protocol. One common communications protocol is the asynchronous transfer mode (ATM) protocol. The ATM protocol defines the rules for transferring data across a network in 53-byte cells that include a 48-byte data field and a 5-byte header.
FIG. 1 shows a perspective view that illustrates a prior-art, backplane-based communications system 100. As shown in FIG. 1, communications system 100 includes a backplane 110, and a number of electronics cards 112 that are plugged into backplane 110. The electronics cards 112, in turn, include a master electronics card 112A, and a number of slave electronics cards 112B. (Only one slave electronics card 112B is shown in FIG. 1 for the sake of clarity.)
Master electronics card 112A, in turn, includes a bus circuit 112C that generates master data and control signals, and receives slave data and control signals. Similarly, the slave electronics cards 112B include a bus circuit 112D that generates the slave data and control signals, and receives the master data and control signals.
Backplane 110 also includes a first MDTL 114 that has a number of metal lines, and a second MDTL 116 that has a number of metal lines. First MDTL 114 supports a downstream bus, while second MDTL supports an upstream bus. In addition, backplane 110 has a number of connecters 118 that are connected to the first and second MDTLs 114 and 116. The connectors 118 are uniformly distributed along the length of the first and second MDTLs 114 and 116 to have, for example, a 2.54 cm (one inch) spacing. As shown in FIG. 1, master electronics card 112A and the slave electronics cards 112B are plugged into the connectors 118.
FIG. 2 shows a block diagram that illustrates bus circuit 112C of master electronics card 112A. As shown in FIG. 2, bus circuit 112C has a clock driver 210 that outputs a downstream clock signal DSCLK, and a framing driver 212 that outputs a framing signal FSYNC to the slave electronics cards 112B. The framing signal FSYNC has a series of framing pulses that are referenced to the downstream clock signal DSCLK.
As further shown in FIG. 2, bus circuit 112C of master electronics card 112A also includes 16 downstream data drivers 214 that output 16 downstream data signals DSD0-DSD15 to 16 corresponding slave electronics cards 112B such that each slave electronics card 112B receives a different downstream data signal DSD during each framing period.
Each data driver 214 serially outputs a downstream data signal DSD such that each byte of data has bits of data that are output during different periods of the downstream clock signal DSCLK. The data drivers 214 can be implemented as inverting backplane transceiver logic (BTL) drivers.
In addition, bus circuit 112C of master electronics card 112A also has a grant driver 216 that drives a bus grant signal USGNT to the slave electronics cards 112B during each framing period. The bus grant signal USGNT grants a slave electronics card 112B control over the upstream bus to transmit eight upstream data signals USD[7:0] during the next framing period.
FIGS. 3A-3F show timing diagrams that illustrate the operation of bus circuit 112C of master electronics card 112A. In addition, FIGS. 4A-4D show timing diagrams that further illustrate the operation of bus circuit 112C. As shown in the figures, clock driver 210 outputs the downstream clock signal DSCLK, which has a period T, while framing driver 212 outputs the framing signal FSYNC with a series of pulses. The series of pulses define a series of time slots where each pair of adjacent pulses defines a time slot.
In the present example, the downstream clock signal DSCLK is output with a frequency of 77.76 Mhz, and the framing signal FSYNC is output as a pulse that has a logic high that lasts for seven downstream clock periods, and a logic low that lasts for 212 downstream clock periods.
Further, each downstream data signal DSD has 424 bits of data (b′0-b′423) that are transmitted during the 212 downstream clock periods that the framing signal FSYNC is low. The 424 bits of data equal 53 eight-bit bytes which, in turn, is the required size of an ATM cell. As a result, each driver 214 outputs a data signal DSD between framing pulses that represents one ATM cell.
As shown in FIGS. 3A-3F, each data driver 214 outputs the first data bit b′0 of the 424 data bits following the rising edge of the downstream clock signal DSCLK that immediately precedes the falling edge of the framing signal FSYNC. As a result, the leading edge of first data bit b′0 slightly trails the rising edge of the clock signal DSCLK, but is substantially coincident with the falling edge of the framing signal FSYNC.
In addition, each data driver 214 outputs the second data bit b′1 following the next falling edge of the downstream clock signal DSCLK. This sequence continues until the last data bit b′423 of the 424 bits is output following the falling edge of the downstream clock signal DSCLK that immediately precedes the rising edge of the framing signal FSYNC.
As a result, the leading edge of last data bit b′423 slightly trails the falling edge of the clock signal DSCLK, while the trailing edge of the last data bit b′423 is substantially coincident with the rising edge of the framing signal FSYNC. The rising edge of the framing signal FSYNC indicates the end of one ATM cell, while the falling edge of the framing signal FSYNC indicates the beginning of the next ATM cell.
Thus, each driver 214 outputs a bit of data during each half period of the downstream clock signal DSCLK, following both the rising and falling edges of the clock signal DSCLK. As a result, since each driver 214 outputs two bits during each of the 424 clock periods, and data is transferred every 424 clock periods out of every 431 clock periods (no data is transferred during the seven clock periods that the framing signal FSYNC is high), each driver 214 has a serial data rate of approximately 152 Mbps.
Included within the 424 bits of data is a header error control (HEC) that detects errors in the header of the ATM cell. Each driver 214 computes the HEC for all of the to-be-transmitted ATM cells. The HEC is computed per the ATM protocol on the first four bytes of a cell, and is inserted as the fifth byte of the cell.
Returning to FIG. 2, bus circuit 112C of master electronics card 112A also has eight data receivers 220 that receive the eight upstream data signals USD[7:0] over the upstream bus from the slave electronics cards 112B. The data receivers 220 receive the upstream data signals USD[7:0] in parallel such that each byte of data has bits of data that are all received during the same period of the downstream clock signal DSCLK.
Master electronics card 112A further includes a clock receiver 222 that receives an upstream clock signal USCLK from the slave electronics cards 112B. The upstream clock signal USCLK is used to receive other upstream signals. In the present example, the data receivers 220 utilize the upstream clock signal USCLK to clock the incoming upstream data signals USD[7:0].
Further, bus circuit 112C of master electronics card 112A includes a grant engine 224 that identifies a slave electronics card 112B from a number of slave electronics cards 112B that is to receive control over the upstream bus during a subsequent framing period. Once identified, grant engine 224 outputs a bus grant signal USGNT that identifies the slave electronics card 112B to grant driver 216. As noted above, grant driver 216 drives the bus grant signal USGNT to the slave electronics cards 112B.
With respect to FIG. 3D, the bus grant signal USGNT generated by driver 216 includes 32 bits of grant data bg′0-bg′31 that are output following each falling edge of the framing pulse FSYNCH. Each bit of grant data, in turn, corresponds with a slave electronics card 112B. In addition, only one bit of the grant data has a logic high during each framing period.
Thus, when the first grant bit bg′0 corresponds with a first slave card 112B that has been configured to be identified as slot 0 on backplane 110, the first slave card 112B is granted control of the upstream bus by grant engine 224 for the next framing period by outputting the first grant bit bg′0 as a logic high and the remaining grant bits bg′1-bg′31 as logic lows during the current framing period.
Similarly, when the second grant bit bg′1 corresponds with a second slave card 112B that has been configured to be identified as slot 1 on backplane 110, the second slave card 112B is granted control of the upstream bus during the next framing period by outputting the first grant bit bg′0 as a logic low, the second grant bit bg′1 as a logic high, and the remaining grant bits bg′2-bg′31 as logic lows during the current framing period.
Returning to FIG. 2, master electronics card 112A also has a grant table 228 that is connected to grant engine 224. Table 1 illustrates an example of grant table 228.
TABLE 1Slot Number133. . .2
Each row of Table 1 corresponds with a time slot. In the present example, Table 1 has 40 rows that correspond with 40 time slots. Each row/time slot, in turn, has an associated slot number that identifies a slave electronics card 112B on backplane 110. Thus, grant engine 224 reads from Table 1 and grants the upstream bus in cycles of forty time slots (framing periods), from time slot 0 to time slot 39 (see also FIG. 4A).
In the Table 1 example, the slave electronics card identified as slot 1 receives the first grant, the slave electronics card identified as slot 3 receives the 2nd and 3rd grants, and the slave electronics card identified as slot 2 receives the 40th grant. During this forty-frame cycle, grant engine 224 can alternately grant the bus to a single slave forty times, zero times, or any number of times in between.
In operation, during time slot 0 (frame 0), grant engine 224 reads the associated slot number from the first row of grant table 228. Thus, in the present example, grant engine 224 reads during time slot 0 that the slave electronics card identified as slot 1 is to receive a frame. In response, grant engine 224 generates a bus grant signal USGNT that grants control over the upstream bus during a subsequent framing period to the slave electronics card 112B that is identified as slot 1.
During time slot 1 (frame 1), grant driver 216 drives the grant signal USGNT to the slave electronics card that is identified as slot 1. Further, grant engine 224 reads from the second row of grant table 228 that the slave electronics card identified as slot 3 is to receive a frame. In response, grant engine 224 generates a bus grant signal USGNT that grants control over the upstream bus to the slave electronics card 112B that is identified as slot 3.
During time slot 2 (frame 2), the slave electronics card that is identified as slot 1 transmits upstream data signals USD[7:0] over the upstream bus to the data receivers 220. Further, grant driver 216 drives the grant signal USGNT to the slave electronics card that is identified as slot 3.
In addition, grant engine 224 reads from the third row of grant table 228 that the slave electronics card that is identified as slot 3 is to again receive a frame. In response, grant engine 224 again generates a bus grant signal USGNT that grants control over the upstream bus to the slave electronics card 112B that is identified as slot 3.
During time slot 3 (frame 3), the slave electronics card that is identified as slot 3 transmits upstream data signals USD[7:0] over the upstream bus to the data receivers 220. Grant engine 224 continues to grant control over the upstream bus to the slave electronics card 112B that is associated with each succeeding time slot until grant engine 224 has stepped through each row in Table 1. After this, grant engine 224 returns to the top of Table 1 and again reads the slot number from the first row of grant table 228.
When a slave electronics card 112B receives a grant and takes control of the upstream bus, the slave electronics card 112B outputs ATM data cells to the data receivers 220 when data is present, and outputs ATM idle cells to the data receivers 220 when all of the data has been previously output and data is no longer present.
An idle cell can include, for example, all zeros. Further, an idle cell has a virtual path indicator (VPI) and a virtual connection indicator (VCI) that are both set to zero. As a result, an idle cell passes through an inverting BTL driver as a high logic level, which is the off state or low power state for an inverting BTL driver.